NVIDIA NVHBM Moves Memory Controller Into the HBM Stack
NVIDIA's custom NVHBM technology promises 30% more bandwidth than HBM4E, 15% lower power draw, and up to 25% more usable compute die area by relocating the memory controller off the GPU die entirely.
The Memory Controller Moves Out
For decades, the standard arrangement in GPU design has been straightforward: the memory controller lives on the compute die, and the memory stacks sit nearby. NVIDIA just announced it is rethinking that arrangement entirely.
The company revealed NVHBM, a custom high-bandwidth memory technology that relocates the memory controller off the compute die and embeds it directly into the HBM base die itself. As reported by TechPowerUp, NVIDIA plans to use the technology in future GPUs and is also opening it up to third-party XPU customers through NVLink Fusion.
The logic behind the move is pretty clean. Every square millimeter dedicated to memory control circuitry on a compute die is a millimeter that cannot be used for actual computation. By offloading that controller into the 3D HBM stack, NVIDIA says it can reclaim up to 25% more usable compute die area on the processing unit.
The Numbers Behind the Shift
NVIDIA is making specific performance claims for NVHBM, and they are hard to ignore. Compared to standard HBM4E, the company says NVHBM delivers up to 30% more memory bandwidth and 15% lower HBM power consumption.
To put those figures in context: at Hot Chips 2026 on Monday, Samsung confirmed it is preparing to ship HBM4E running at 16 Gbps per pin, up from 14 Gbps on its current HBM4E. That next-generation speed translates to 4 TB/s per stack across 2,048 pins. Apply the 30% bandwidth improvement NVIDIA is claiming, and a single NVHBM stack could theoretically reach around 5.2 TB/s, according to TechPowerUp’s analysis of the figures.
The area savings come from a redesigned physical memory interface. Standard HBM uses wider interface connections that increase package footprint. NVIDIA’s custom PHY reduces that I/O area by up to 67% compared to JEDEC HBM4E. That narrower interface also simplifies interposer routing, which NVIDIA says frees up to 80% more usable silicon across the layout. Fewer routing constraints matter significantly when you are trying to fit multiple HBM stacks alongside a large compute die on a single package.
Power Savings at Rack Scale
The 15% reduction in power draw is not just about running cooler. NVIDIA frames it primarily as a data center concern. When thousands of compute units are operating simultaneously across hundreds of racks, that thermal headroom translates directly into more compute density per watt.
NVIDIA offered a concrete example in its dedicated blog post: in a hypothetical 1-gigawatt data center using 2,000-watt XPUs, the power savings from NVHBM could enable up to 15,000 additional XPUs within the same power budget. That is the kind of arithmetic that tends to get the attention of hyperscale operators.
The company also announced that NVHBM will be validated across multiple memory vendors, which it says is intended to simplify supplier qualification for customers. Amazon’s Annapurna Labs was named as the first confirmed partner to collaborate on the technology.
What This Means for Future GPU Silicon
For PC gamers and enthusiasts watching this space, NVHBM is most immediately relevant as a data center and XPU story. But NVIDIA has confirmed the technology will appear in future GPUs, which means the architectural shift will eventually reach consumer products as well.
The combination of reclaimed compute area, lower power, and higher bandwidth on the same package represents a meaningful departure from how high-end GPU silicon has been built. Moving the memory controller into the stack rather than onto the die is an architectural bet that the efficiency gains justify the added complexity of the custom HBM implementation. Based on NVIDIA’s stated figures, the company clearly believes the math works out in its favor.
What is NVIDIA NVHBM?
NVHBM is a custom high-bandwidth memory technology from NVIDIA that moves the memory controller into the HBM base die rather than keeping it on the compute die. NVIDIA announced the technology and says it will be used in future GPUs and made available to third-party XPU customers through NVLink Fusion.
How much faster is NVHBM compared to HBM4E?
According to NVIDIA, NVHBM delivers up to 30% more memory bandwidth than standard HBM4E. Using Samsung's announced HBM4E speed of 4 TB/s per stack as a baseline, a single NVHBM stack could theoretically reach around 5.2 TB/s.
What are the power and area benefits of NVHBM?
NVIDIA claims NVHBM uses 15% less power than standard HBM4E and frees up to 25% more usable compute die area. The custom PHY reduces I/O area by up to 67% compared to JEDEC HBM4E and frees up to 80% more usable silicon across the interposer layout.
Who are the first partners for NVHBM?
NVIDIA says NVHBM will be validated across multiple memory vendors. Amazon's Annapurna Labs was announced as the first confirmed partner to collaborate on the technology.